Voltage regulators are monitored with respect to their output voltage in safety-relevant systems. If the input voltage of such a voltage regulator slowly decreases, as is possible in buffered energy reserve-based systems (airbag, etc.), the output voltage is reduced when a drop below a minimal control input voltage occurs. When the output voltage reaches a lower monitoring limit, a RESET signal (for the identification of an undervoltage at the regulator output) is triggered, which may be used as a monitoring signal to control consumers connected to the regulator. This RESET (i.e., the monitoring signal RESET) resets all digital states to the starting state and stops clocked program processing steps and digital state machines. This also results in a synchronous load reduction of the regulator (regulator output current is synchronously reduced). Since voltage regulators have a finite internal resistance when leaving the voltage regulating range to the downside, a regulator output current reduction in this range results in an increase in the control output voltage due a decreasing regulator drop. As a result, the RESET undervoltage limit is again exceeded, multiple RESET pulses being generated in particular in the case of strong regulator input buffering (e.g., when the energy reserve is high).